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CMX625 isdn ta pots interface ? 2001 consumer microcircuits limited d/625/2 july 2001 advance information features applications ? ? ? ? spm and ringing voltage generators ? ? ? ? isdn ntus with analogue ports ? ? ? ? integrated dtmf decoder/encoder ? ? ? ? isdn line cards ? ? ? ? v.23/bell 202 fsk/tone generator ? ? ? ? wireless local loop termination cards ? ? ? ? selectable a-law/-law pcm codec ? ? ? ? isdn terminals with additional pots ports ? ? ? ? iom-2 interface terminal mode and ? ? ? ? pc based isdn cards with telephone ports non-terminal mode (line card mode) ? ? ? ? billing/spm systems iom is a trademark of siemens ag 1.1 brief description the CMX625 is an integrated telecom tone generator, dtmf encoder/decoder and pcm codec-filter designed for isdn interfaces, wireless local loop and other digitised speech systems. the tone generator covers a wide range of pre-programmed tones used in analogue phone systems. three outputs are provided: ringing signals, in-band tones or fsk data, and 12khz/16khz subscriber metering pulses. the pcm codec-filter performs voice digitisation and reconstruction and incorporates band limiting and smoothing with selectable a-law or -law companding following itu-t recommendation g.711. the dtmf decoder presents the serial bus interface with the dtmf dialling information received from the telephone user and the tone generator sends the appropriate dtmf tones to this pots interface. other tone standards supported are: fax and modem ?answer? and ?originate?, itu-t ?r1? and ?r2? signals, dual tones for cidcw and 'on-hook' signalling systems and sufficient tones for simple melody generation. the iom ? -2 (isdn oriented modular revision 2) industry standard serial bus provides the digital interface to other telecommunications ics and supports both terminal and non-terminal (or line card) modes. the CMX625 is compatible with the cmx635 isdn subscriber processor and can be used to provide the additional pots port. it is available in both dip and ssop packages. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 2 d/625/2 contents section page 1.1 brief description ..................................................................................... 1 1.2 block diagram ......................................................................................... 3 1.3 signal list ................................................................................................ 4 1.4 external components ............................................................................. 6 1.5 general description ................................................................................ 7 1.5.1 iom?-2 serial bus interface ..................................................... 7 1.5.2 terminal mode (te).................................................................... 8 1.5.3 non-terminal mode (non-te) ................................................. 10 1.5.4 monitor channel handshake protocol................................... 11 1.5.5 monitor channel identification command ............................ 13 1.5.6 pcm codec-filter ..................................................................... 13 1.5.7 rx input amplifier .................................................................... 14 1.5.8 tx output buffer ...................................................................... 14 1.5.9 tone/fsk encoder and tone encoder .................................. 14 1.5.10 spm generator ......................................................................... 17 1.5.11 transmit signal control .......................................................... 17 1.5.12 tx uart .................................................................................... 18 1.5.13 dtmf tone decoder ................................................................ 19 1.5.14 register set .............................................................................. 20 1.5.15 programming the CMX625 ...................................................... 20 1.5.16 glossary.................................................................................... 22 1.6 application notes.................................................................................. 23 1.6.1 telecom tones ......................................................................... 23 1.7 performance specification................................................................... 27 1.7.1 electrical performance ............................................................ 27 1.7.2 packaging ................................................................................. 33 www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 3 d/625/2 1.2 block diagram v dd v bias rxn v ss rxp rxo tx uart status & irq status & irq dtmf to n e decoder bus fsc dcl du dd irqn iom -2 serial bus interface ? fsk / tones tx registers setup & mode registers status register pcm codec registers rom tone encoder tone / fsk encoder tx signal control ring pcm adc a-law / -law tonefsk vbias dac out txon txo txn sa2 sa1 sa0 te/nte ds interrupt generator pcm dac a-law / -law tx output buffer enable rx input amplifier enable analogue loopback spm generator spm reset figure 1 block diagram www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 4 d/625/2 1.3 signal list CMX625 d5/p4 signal description pin no. name type 1 fsc i/p the iom-2 frame synchronisation clock. this is an 8khz clock indicating the start of the frame. fsc is generated by the upstream device. see section 1.5.1, 1.5.2 and 1.5.3. 2 dcl i/p the iom-2 data clock. it is used to clock data on and off the bus and operates at 1.536mhz for terminal mode (te) or 4.096mhz for non-terminal mode (non-te or line card mode). dcl is generated by the upstream device. when the bus is deactivated, dcl is held in a low state. see section 1.5.1, 1.5.2 and 1.5.3. 3 dd bi the iom-2 data downstream, receives data from the network. when the bus is deactivated or when data is not being transmitted, dd is high impedance. the ic channel bus reversal (te mode only) allows ic1 and ic2 data to be transmitted on the dd pin. see section 1.5.1, 1.5.2, 1.5.3 and 1.5.6. an external pull-up resistor is required. 4 du bi the iom-2 data upstream, transmits data to the network. when the bus is deactivated or when data is not being transmitted, du is high impedance. the ic channel bus reversal (te mode only) allows ic1 and ic2 data to be received on the du pin. see section 1.5.1, 1.5.2, 1.5.3 and 1.5.6. an external pull-up resistor is required. 5 te/nte i/p the iom-2 two modes of operation: te = 0 selects terminal mode. nte = 1 selects non-terminal mode or line card mode. see section 1.5.1, 1.5.2 and 1.5.3. 6 sa0 i/p ) the iom-2 slot address, provides one of 8 unique 7 sa1 i/p ) addresses. it allows the device to be individually 8 sa2 i/p ) addressed when more than one device is connected ) to the iom-2 bus. see section 1.5.2 and 1.5.3. 9 ds i/p the iom-2 device select pin (nte mode only). allows two CMX625 devices sharing a slot address to be individually addressed. ds = 0 selects device one. ds = 1 selects device two. see section 1.5.2 and 1.5.3. 10 reset i/p the external reset pin clears all the registers. (reset=1) 11 irqn o/p a ?wire-orable? output interrupt request. this output is pulled down to v ss when active and is high impedance when inactive. an external pull-up resistor is required. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 5 d/625/2 CMX625 d5/p4 signal description pin no. name type 12 v ss power the negative supply rail (ground). 13 rxp i/p the non-inverting input of the receive op-amp. 14 rxn i/p the inverting input of the receive op-amp. 15 rxo o/p the output of the receive op-amp. 16 v bias o/p an internally generated bias voltage of v dd /2, except when the device has been reset, v bias will discharge to v ss. it should be decoupled to v ss by a capacitor mounted close to the device pins. 17 tonefsk o/p the sinewave output of the tones and fsk signal generators. 18 txo o/p the output of the buffer amplifier. 19 txn i/p the inverting input to the buffer amplifier. 20 txon o/p the inverted output of the buffer amplifier. 21 dac out o/p the output from the digital-to-analogue converter. 22 ring o/p the square, trapezoidal and sinusoidal wave output from the ringing signal generator. 23 spm o/p the sinewave output of the spm signal generator. 24 v dd power the positive supply rail. levels and thresholds within the device are proportional to this voltage. it should be decoupled to v ss by a capacitor mounted close to the device pins. notes: i/p = input o/p = output bi = bi-directional n/c = no (external) connection this device is capable of detecting and decoding small amplitude signals. to achieve this v dd and v bias decoupling and protecting the receive path from extraneous in-band signals are very important. it is recommended that the printed circuit board is laid out with a ground plane in the CMX625 area to provide a low impedance connection between the v ss pin and the v dd and v bias decoupling capacitors. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 6 d/625/2 1.4 external components 16 21 20 15 19 24 14 18 23 13 17 22 1 2 3 4 5 9 6 10 7 11 8 12 irqn te/nte fsc dd sa1 sa2 dcl du sa0 ring rxo tonefsk v bias txo txn txon rxp dac out rxn r1 c1 c2 v ss v ss v ss v ss v dd v dd v dd CMX625 ds iom -2 bus interface tm r2 r3 c3 c4 rx in v bias tx in r4 r5 c5 r6 v dd r7 spm reset c6 figure 2 recommended external components r1, r4 100k ? c1, c2 1.0f r2, r3 110k ? c3 100nf r5 56k ? c4, c5 220pf r6, r7 note 2 c6 22nf resistor 1%, capacitors 5% unless otherwise stated. note: 1. the recommended component values, c3 to c6 and r2 to r5 and tolerances are essential to meet the itu-t recommendation g.172 filter specification. see figure 12. 2. r6, r7 = 750 ? with 5v supply. r6, r7 = 470 ? with 3.3v supply. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 7 d/625/2 1.5 general description the CMX625 is a telecom tone generator, dtmf tone encoder/decoder and pcm codec-filter for isdn interfaces. the pcm codec-filter performs voice digitisation and reconstruction and incorporates encoder bandpass and decoder lowpass filters with pre and post-filtering with selectable a-law and -law companding following itu-t recommendation g.711. the device has separate output ports for the four different classes of signals encoded. these include ringing signals, in-band tones or fsk data at 1200bps, high frequency metering pulses (spm tones) and dac signals. it has a transmit level attenuator for in-band tones or fsk data and an envelope control for spm tones. the device also has an uncommitted tx output buffer for filtering and impedance matching. the functions are controlled via an iom-2 serial bus interface. frequency and timing accuracy of the CMX625 is supplied by the data clock (dcl) of the iom-2 serial bus interface. if the bus is deactivated, dcl is held in a low state. the CMX625 can be reset externally by driving the reset pin low. it resets all the internal register bits and ensures that the interface always starts from a known state. the device can also be reset by issuing a reset command. see section 1.5.14. commands to enable and disable individual functions are also shown in this section. approximately 50ms should be allowed for the tx dc level to settle at v bias before enabling the tx functions (set bit 6 of the mode register to ?1?) after the CMX625 has been reset. 1.5.1 iom-2 serial bus interface the iom ? -2 (isdn oriented modular revision 2) is an industry standard serial bus for interconnecting telecommunications ic?s. (refer to the iom-2 interface reference guide, industry standard bus by advanced micro devices). the bus is an evolution of the iom ? interface and is also known as the gci (general circuit interface). the iom-2 bus provides a symmetrical full duplex communication link, containing user data, control/programming and status channels. there are two basic modes of operation known as terminal mode (te mode) and non-terminal mode (non-te or line card mode). these modes differ in the frame structure and data rate. the frame rate remains at 8khz for each mode. the CMX625 acts as a timing and control slave to the upstream device. the various channels are time multiplexed over a basic four wire serial interface, namely fsc, dcl, dd and du. frames are delimited by an 8khz frame synchronisation clock (fsc) which is generated by the upstream device. the data clock (dcl) clocks data on and off the bus and runs at either 1.536mhz (te mode) or 4.096mhz (non-te mode). it is always generated by the upstream device. data downstream (dd) receives data from the network. data upstream (du) transmits data to the network. when the bus is deactivated or when data is not being transmitted, dd and du is held in a high impedance state. the dd and du bus are driven by open drain transistors such that all dd?s and du?s can be connected together. bus reversal (in te mode) allows the dd and du pins to be both inputs and outputs in the ic1 and ic2 channels. it allows use of the CMX625 with post processing devices that are iom-2 compliant. when other devices are connected to the iom-2 bus the three slot address pins (sa0, sa1 and sa2) provide a unique address, allowing the CMX625 to be individually addressed. the device select pin (ds) allows two CMX625 devices sharing a slot address to be individually addressed in non-te mode. the remote digital iom loopback is enabled when bit 3 of the iom control register is set to ?1?. this loops back the data arriving on the iom-2 bus and sends it back again. unused bits in the frame structure are ignored if not required by the CMX625. these bits will be set to '1' when the frame is transmitted upstream. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 8 d/625/2 1.5.2 terminal mode (te) terminal mode (te) frame structure consists of 3 channels of 4 bytes each repeated at 8khz, i.e. 96 bits in 125 s or a data rate of 768kbps. the data clock (dcl) operates at twice the data rate, i.e. 1.536mhz. figure 3 shows the te mode frame structure. 125s channel 0 channel 1 channel 2 b1 b2 mon0 c/i0 d m r m x channel 0 ic1 ic2 mon1 c/i1 m r m x channel 1 tic channel 2 not used not used not used du/dd fsc dcl m s b l s b fsc = 8khz dcl = 1.536mhz dd, du = 768kbps figure 3 terminal mode frame structure ?channel 0? is used for passing user data (2b+d channels) and controlling (mon0 and c/i0) the layer 1 transceiver. only ?channel 1? is used by the CMX625. ?channel 2? is reserved for d channel arbitration. the 12 byte frame contains the following channels: (i) the ?b? channels consist of two 64kbps data channels, labelled b1 and b2, and transfer b channel data to and from the network. (ii) the ?monitor? channels consist of two programming channels, labelled mon0 and mon1. each channel consists of 8 bits of data and has two associated pair of handshake bits that control data flow, mx and mr (monitor transmit and receive). the handshake procedure is described in section 1.5.4. the mon1 channel is used for programming and controlling devices attached to the iom-2 interface. the CMX625 is programmed via the mon1 channel (see section 1.5.15). the mon0 channel is not used. monitor channel contention is avoided by a ?speak when spoken to? system whereby the CMX625 is given a unique address, programmed with the 3 slot address pins (sa0 to sa2) and 1 device select pin (ds) and only responds when that address is broadcast by the master device (see section 1.5.14). the monitor channel address byte is shown below: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mon channel address byte 1 slot address sa2 slot address sa1 slot address sa0 device select ds 0 0 0 www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 9 d/625/2 the CMX625 cannot initiate mon communication directly in a multi-slave application. each slave must monitor the mon channel for its unique address in the first byte before processing the following command. each slave can therefore only drive the du mon channel when specifically requested to by the master. (iii) the ?d? channel consists of two bits providing 16kbps for carrying d channel user data. this channel is not used by the CMX625. (iv) the ?command/indicate? channels, labelled c/i0 and c/i1, provide real time status information between devices connected via the iom-2 bus. the c/i0 in channel 0 consists of 4 bits and the c/i1 in channel 1 is 6 bits wide. the c/i0 in channel 0 is not used. the c/i1 channel is shared by all devices on the iom-2 bus with no mechanism for determining and resolving contention. if multiple slave devices are expected to drive the c/i1 channel then care must be taken to allocate different bits to each device. an example of c/i1 channel usage would be 6 slave devices each allocated one of the 6 c/i1 bits. when a slave requires attention it asserts its own bit, which is detected by the master as a c/i1 value change (generating a processor interrupt). the processor would then initiate mon1 communications with the appropriate slave and service its request. this is an example of one usage, but the c/i1 bits may be used for any real time command/indicate purpose dependent on system design and number of slaves on the iom-2 bus. the c/i1 channel output control code is encoded as follows (bits 0, 1 and 2 of the iom control register): c/i1 channel output control code (iom control register, bits 2, 1 and 0) c/i1 channel output bit content 0 0 0 c/i1 bits 5-0 = all logic ?1?, i.e. c/i1 output disabled 0 0 1 interrupt request (logic ?0?) on c/i1 bit 0 ) 0 1 0 interrupt request (logic ?0?) on c/i1 bit 1 ) 0 1 1 interrupt request (logic ?0?) on c/i1 bit 2 ) all other bits logic ?1? 1 0 0 interrupt request (logic ?0?) on c/i1 bit 3 ) 1 0 1 interrupt request (logic ?0?) on c/i1 bit 4 ) 1 1 0 interrupt request (logic ?0?) on c/i1 bit 5 ) 1 1 1 status register bits 7-2 on c/i1 bits 5-0 code ?000? is provided to disable drive of the c/i1 channel for use when multiple slaves have completely utilised the c/i1 channel resource. the interrupt mask register settings are ignored and the c/i1 bits are set to logic ?1?. for codes ?001? to ?110? a logic ?0? (interrupt request) is driven onto the appropriate c/i1 bit when the status register bits contain an unmasked logic ?1? (set by the interrupt mask register). this allows other devices to use the remaining c/i bits for their own purposes. the master device would use the change of the appropriate c/i bit to initiate a status register read from the CMX625. code ?111? and an unmasked status register (interrupt mask bits 2 to 7 are set to ?1?) allows the most significant 6 bits of the status register to be driven onto the c/i1 channel directly for use when the CMX625 is the only slave utilising the c/i channel. if any of the status bits are masked, by setting the equivalent bit in the mask register to ?0?, then a logic ?0? will be routed to the appropriate c/i1 bit and will not change. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 10 d/625/2 (v) the ?intercommunication channel? consists of two 64kbps data channels, labelled ic1 and ic2, and provide additional communications paths between devices other than the layer 1 device (data to and from the layer 1 device is transferred over the b channels). (vi) the ?tic? (terminal ic) bus is used for connecting more than one device to the d and c/i0 channels in channel 0. the tic bus is not used by the CMX625. 1.5.3 non-terminal mode (non-te) the non-te mode (line card mode) frame structure consists of up to 8 channels of 4 bytes each repeated at 8khz, i.e. 256 bits in 125 s or a data rate of 2048kbps for 8 channel frames. the data clock (dcl) operates at twice the data rate, i.e. 4.096mhz. figure 4 shows the non-te mode frame structure. m x m r l s b m s b m x m r l s b m s b ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 dd ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 du fsc dcl 125s b1 b2 monitor c/i b1 b2 monitor c/i d for analogue lines for isdn lines fsc = 8khz dcl = 4.096mhz dd, du = 2048kbps figure 4 non-terminal mode frame structure in non-te mode the iom-2 bus time multiplexes data, control and status information for up to eight iom-2 devices or up to 16 codec-filters over a single full duplex interface. the frames are subdivided into 8 channels, with one channel being dedicated to each iom-2 device or pair of codecs. each device on the iom-2 bus is assigned a slot address and only transmits to and receives from that time slot. pins sa0, sa1 and sa2 on the CMX625 are used to program the slot address. outside the allocated slot the transmit drivers will be set to high impedance to allow other devices to transmit in their own time slot. to allow two CMX625 devices to share the same slot a device select pin (ds) is made available. this pin forms part of the monitor channel address byte along with the slot address pins and allows either of the two devices sharing a slot to be individually addressed. see section 1.5.2, part (ii) mon channel address byte. this mechanism allows both the b1 and b2 data from the same time slot to be utilised by different devices. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 11 d/625/2 each channel consists of the following 4 bytes: (i) the first two bytes consist of two 64kbps data channels, labelled ?b1? and ?b2?, and transfer b channel data to and from the network. (ii) the third byte, labelled ?monitor?, is used for programming and controlling devices attached to the iom-2 interface. the data structure within the monitor channel is not defined and will be device specific. the CMX625 is programmed via the monitor channel (see section 1.5.15). (iii) in digital applications (isdn line cards) the fourth byte contains two bits for the 16kbps ?d? channel, four ?command/indicate? (c/i) bits for real time status information and two handshake bits for supporting the handling of the monitor channel, labelled ?mr? and ?mx? (monitor transmit and receive). the handshake procedure is described in section 1.5.4. in analogue applications (analogue line cards) there is no 'd' channel in the fourth byte so the adjacent c/i channel is increased to 6 bits. the c/i1 channel bits are used in the same way as for terminal mode. 1.5.4 monitor channel handshake protocol the monitor channel operates on an event driven basis. while data transfers on the bus take place synchronised to the frame sync, the flow of data is controlled by a handshake procedure using the outgoing mx (monitor transmit) and incoming mr (monitor receive) bits. data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted repeatedly (once per 8khz frame) until the transfer is acknowledged (ack) via the mr bit. the actual data rate is not fixed but is dependent upon the response speed of the transmitter and receiver. the protocol is applicable to both te and non-te modes. byte 1 byte 2 byte 3 byte n ack ack ack ack 125s eom mr mx data figure 5 monitor handshake timing (general case) figure 5 shows the general case for monitor handshake timing. the first byte of data is placed on the bus and mx is activated (low). mx remains active and the data remains valid until an inactive-to-active transition of mr is received, indicating that the receiver has read the data off the bus. the next byte is placed on the bus after the inactive-to-active transmission of mr, as early as the next frame (there is no limit to the maximum number of frames). at the time that the second byte is transmitted, mx is returned inactive (high) for one frame (mx inactive for more than one frame indicates an end of message). in response to mx going active (low), mr will be deactivated (high) for one frame (the mx inactive to mr inactive delay can be any number of frames). this procedure is repeated for each additional byte. the transmitter sends an end of message (eom), after the last byte of data has been transmitted, by not reactivating mx after deactivating it. the receiver can hold off the transmitter by keeping mr active until the receiver is ready for the next byte. the transmitter will not start the next transmission cycle until mr goes inactive. the transmitter is able to abort a transmission by holding mx inactive (high) for two or more frames, this will generate an interrupt when the interrupt mask register bit 3 is unmasked (logic ?1?) and bit 3 of the status register will be set to ?1?. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 12 d/625/2 figure 6 shows the monitor channel handshake procedure. mx = monitor transmit bit, active low. mr = monitor receive bit, active high. md = monitor data figure 6 monitor channel handshake procedure figure 7 shows the maximum speed case for monitor handshake timing. the transmitter can be designed for a higher data throughput than is provided by the general case. the transmitter can deactivate (high) mx and transmit new data one frame after mr is deactivated. in this way, the transmitter is anticipating that mr will be reactivated one frame after it is deactivated, minimising the delay between bytes. mr being held inactive (high) for two or more frames indicates an abort is being signalled by the receiver. byte 1 byte 2 byte 3 byte n ack ack ack ack eom mr mx data figure 7 monitor handshake timing (maximum speed case) the abort is a signal from the receiver to the transmitter indicating that data has been missed. the receiver is able to abort a transmission by holding mr inactive (high) for two or more frames in response to mx going active. an abort from the receiver will generate an interrupt when the interrupt mask register bit 2 is unmasked (logic ?1?) and bit 2 of the status register will be set to ?1?. figure 8 shows a monitor abort request from the receiver. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 13 d/625/2 byte 1 byte 2 abort request eom mr mx data figure 8 abort request from the receiver 1.5.5 monitor channel identification command in order to be able to identify different devices on the iom-2 bus, an identification command is sent. this allows the software to identify different manufacturer's devices on the bus. the identification sequence is usually done once, when the device is connected for the first time. a device requesting the identity of a connected CMX625 will transmit the following 2 byte command: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit 0 dd 1 st byte 1 sa2 sa1 sa0 ds 0 0 0 dd 2 nd byte 0 0 0 0 0 0 0 0 the CMX625 responds by transmitting: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit 0 du 1 st byte 1 sa2 sa1 sa0 ds 0 0 0 monitor channel address byte du 2 nd byte 1 0 0 1 1 0 0 1 device identification byte sa(2-0) = slot address, ds = device select (see sections 1.5.2 and 1.5.3). see section 1.5.14 for the device identification register. 1.5.6 pcm codec-filter the pcm codec-filter performs voice digitisation and reconstruction and incorporates encoder bandpass and decoder lowpass filters with pre and post-filtering with selectable a-law and -law companding. in each case the coder and decoder process a companded 8-bit pcm word following itu-t recommendation g.711 for a-law and -law conversion. the encoder bandpass filter and decoder lowpass filter provide passband flatness and stopband rejection according to itu-t recommendation g.712. the lowpass filter contains the required (sin x)/x compensation. the overall filter characteristics of the channel are shown in figure 12. the pcm codec-filter block is enabled or disabled by bit 7 of the codec control register. the companding law is selected by bit 6. when this bit is a ?0?, a-law companding is selected (used in europe) and when this bit is a ?1?, -law is selected (used in the usa and japan). the pcm codec channel routeing is shown in the table below for normal operation and bus reversal. in ?normal? operation, bit 4 of the iom control register is set to ?0?, the data is transmitted on the data upstream (du) pin and received on the data downstream (dd) pin. bits 6 and 7 of the iom control register select whether the data is transmitted or received on the b1, b2, ic1 or ic2 channels of the iom- 2 bus. the b1 and b2 channels are available in te and non-te mode but the ic1 and ic2 channels are only available in te mode. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 14 d/625/2 codec channel input/output select ic channel bus reversal (iom control register bit 4) codec channel select (iom control register, bits 7 and 6) codec data from codec data to 0 0 0 b1, dd b1, du normal 0 0 1 b2, dd b2, du 0 1 0 ic1, dd ic1, du 0 1 1 ic2, dd ic2, du 1 0 0 b1, dd b1, du reverse 1 0 1 b2, dd b2, du 1 1 0 ic1, du ic1, dd 1 1 1 ic2, du ic2, dd in terminal mode (te) it may also be necessary to transmit on the data downstream (dd) pin and receive on the data upstream (du) pin during the ic1 and ic2 time slots. this can be achieved by selecting bus reversal and allows use of the CMX625 with post processing devices, such as speech scramblers, that are iom-2 compliant. bus reversal is enabled when bit 4 of the iom control register is set to ?1? and programming the appropriate codec channel select bits 6 and 7 of the iom control register. when bus reversal is active, the master device and any other devices capable of bus reversal, are prohibited from broadcasting in the active ic channel. local analogue codec loopback is enabled when bit 5 of the codec control register is set to ?1?. this internally connects the dac output to the adc input (the connection to the rx amp is broken). data is loaded and read via the iom-2 bus using the channels shown in the above table. 1.5.7 rx input amplifier this amplifier, with suitable external components, is used for adjusting the received signal to the correct amplitude for the dtmf decoder and the pcm analogue-to-digital converter. see figure 2 recommended external components. 1.5.8 tx output buffer this buffer is enabled by bit 7 of the setup register. with suitable external components it can be used for filtering and impedance matching. see figure 2 recommended external components. 1.5.9 tone/fsk encoder and tone encoder these blocks are enabled or disabled by bit 6 of the setup register. when bit 5 of the mode register is set to ?1? then these blocks generate fsk signals as determined by bit 0 of the setup register and the tx data bits from the uart block, as shown in the table below: setup register tone/fsk generator fsk signal frequency fsk signal frequency bit 0 ?0? (space) ?1? (mark) 0 v23 1200bps fsk 2100hz 1300hz 1 bell 202 1200bps fsk 2200hz 1200hz when bit 5 of the mode register is set to ?0?, these blocks generate single or dual tones from the range shown in the tables on the following pages. bit 6 of the mode register is then used to enable or disable the block?s output to the tx signal control, ring and tonefsk outputs. there are four tone fields addressed by bits 0 and 1 of the mode register. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 15 d/625/2 tone field 0, mode register bit 1 and bit 0 = ?0? and ?0? respectively. tx tones register bits 4-7 frequency tx tones register bits 0-3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 252.4 0 0 0 1 * 17.1 0 0 1 0 268.7 0 0 1 0 * 20.5 0 0 1 1 285.3 0 0 1 1 * 24.9 0 1 0 0 315.5 0 1 0 0 * 34.1 0 1 0 1 330.5 0 1 0 1 * 41.0 0 1 1 0 375.2 0 1 1 0 * 51.2 0 1 1 1 404.3 0 1 1 1 - 1 0 0 0 468.0 1 0 0 0 262.9 1 0 0 1 495.8 1 0 0 1 293.6 1 0 1 0 520.6 1 0 1 0 348.2 1 0 1 1 548.0 1 0 1 1 392.6 1 1 0 0 562.8 1 1 0 0 1600 1 1 0 1 578.4 1 1 0 1 1633 1 1 1 0 595.0 1 1 1 0 1827 1 1 1 1 612.5 1 1 1 1 587.2 note: * these outputs are routed to the ring digital output instead of the tonefsk output. any single tone output level at tonefsk output is 0dbm. tone field 1, mode register bit 1 and bit 0 = ?0? and ?1? respectively tx tones register bits 4-7 frequency tx tones register bits 0-3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 120 0 0 0 1 330 0 0 1 0 150 0 0 1 0 416 0 0 1 1 154 0 0 1 1 420 0 1 0 0 250 0 1 0 0 425 0 1 0 1 300 0 1 0 1 433 0 1 1 0 350 0 1 1 0 440 0 1 1 1 360 0 1 1 1 450 1 0 0 0 367 1 0 0 0 460 1 0 0 1 375 1 0 0 1 480 1 0 1 0 380 1 0 1 0 500 1 0 1 1 383 1 0 1 1 600 1 1 0 0 400 1 1 0 0 620 1 1 0 1 450 1 1 0 1 720 1 1 1 0 475 1 1 1 0 930 1 1 1 1 480 1 1 1 1 - www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 16 d/625/2 tone field 2, mode register bit 1 and bit 0 = ?1? and ?0? respectively tx tones register bits 4-7 frequency tx tones register bits 0-3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 700 0 0 0 1 700 0 0 1 0 900 0 0 1 0 900 0 0 1 1 1100 0 0 1 1 1100 0 1 0 0 1300 0 1 0 0 1300 0 1 0 1 1500 0 1 0 1 1500 0 1 1 0 1700 0 1 1 0 1700 0 1 1 1 - 0 1 1 1 - 1 0 0 0 950 1 0 0 0 2100 1 0 0 1 1400 1 0 0 1 2225 1 0 1 0 1800 1 0 1 0 - 1 0 1 1 2130 1 0 1 1 2750 1 1 0 0 697 1 1 0 0 1209 1 1 0 1 770 1 1 0 1 1336 1 1 1 0 852 1 1 1 0 1477 1 1 1 1 941 1 1 1 1 1633 tone field 3, mode register bit 1 and bit 0 = ?1? and ?1? respectively tx tones register bits 4-7 frequency tx tones register bits 0-3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 540 0 0 0 1 540 0 0 1 0 660 0 0 1 0 660 0 0 1 1 780 0 0 1 1 780 0 1 0 0 900 0 1 0 0 900 0 1 0 1 1020 0 1 0 1 1020 0 1 1 0 1140 0 1 1 0 1140 0 1 1 1 - 0 1 1 1 - 1 0 0 0 1380 1 0 0 0 1380 1 0 0 1 1500 1 0 0 1 1500 1 0 1 0 1620 1 0 1 0 1620 1 0 1 1 1740 1 0 1 1 1740 1 1 0 0 1860 1 1 0 0 1860 1 1 0 1 1980 1 1 0 1 1980 1 1 1 0 - 1 1 1 0 - 1 1 1 1 - 1 1 1 1 - www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 17 d/625/2 1.5.10 spm generator this block operates independently and has its own output pin. it can transmit 12khz or 16khz and is controlled by bit 4 of the setup register. bit 7 of the mode register is used to enable or disable this block. the signal has a rise and fall time each of about 4ms. the spm signal rises from the bias level to 0dbm in 16 steps of 2db magnitude, and falls from 0dbm to bias level in 16 steps of 2db magnitude. 1.5.11 transmit signal control this block adjusts the amplitude of the fsk transmit signal output level, the level skew between dtmf tones and the signal routing to the output ports. output signal levels are proportional to v dd . the nominal output signal levels (at 0db attenuation and v dd = 5.0v) are: single tone 0dbm dual tone (per tone) -3dbm dtmf high frequency tone -3dbm dtmf low frequency tone -5dbm fsk signal 0dbm the level attenuator provides for level adjustment from 0db to -14db in -2db steps. the typical level is determined by bits 2 to 4 of the mode register as shown in the table below: mode register signal level adjustment bit 4 bit 3 bit 2 (db) 0 0 0 0 0 0 1 -2 0 1 0 -4 0 1 1 -6 1 0 0 -8 1 0 1 -10 1 1 0 -12 1 1 1 -14 the ring signal is a square, trapezoidal or sinusoidal wave. the square and trapezoidal wave have an amplitude of v dd peak to peak and the sinusoidal wave has an amplitude of ? v dd peak to peak. the trapezoidal ringing waveform has a crest factor (cf) of 1.35. bits 2 and 3 of the setup register select the waveform type as shown in the table below. setup register ring signal select bit 3 bit 2 0 0 square wave 0 1 trapezoidal wave 1 0 sinusoidal wave www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 18 d/625/2 1.5.12 tx uart this block connects the iom-2 serial bus interface to the fsk encoder. the block can be programmed to convert transmit data from 8-bit bytes to asynchronous data characters by adding start and stop bits. the transmit data is then passed to the fsk encoder. data to be transmitted should be loaded, via the iom-2 bus interface, into the tx data register when the tx data ready bit (bit 6) of the status register goes high. it will then be treated by the tx uart block in one of two ways, depending on the setting of bit 1 of the setup register: if bit 1 of the setup register is ?0? (tx sync mode) then the 8 bits from the tx data register will be transmitted sequentially at 1200bps, lsb (d0) first. if bit 1 of the setup register is ?1? (tx async mode) then bits will be transmitted as asynchronous data characters at 1200 bps according to the following format: one start bit (space) eight data bits (d0-d7) from the tx data register, with the lsb (d0) transmitted first one stop bit (mark) failure to load the tx data register with a new value when required will result in bit 7 (tx data underflow) of the status register being set to ?1?. if the ?tx async? mode of operation is selected then a continuous mark (?1?) signal will be transmitted until a new value is loaded into tx data. if the ?tx sync? mode is selected then the byte already in the tx data register will be re-transmitted. figure 9a transmit uart function (async) figure 9b transmit uart function (sync) www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 19 d/625/2 1.5.13 dtmf tone decoder this block is enabled or disabled by bit 5 of the setup register. if disabled, bit 4 and 5 of the status register and bit 0 to bit 3 of the dtmf rx data register are set to ?0? and no interrupts are generated. when bit 5 of the setup register is enabled and bit 4 of the interrupt mask register is set to ?1? (i.e. unmasked) a ?detected tone? generates an interrupt and bit 4 of the status register is set to ?1?. reading the status register clears the irqn output. when bit 5 of the setup register is enabled and bit 5 of the interrupt mask register is unmasked (logic ?1?), a ?status change? of the decoder will generate an interrupt and bit 5 of the status register will be set to ?1?. the validity of the data is indicated by bit 4 of the status register. the decode truth table is shown below. reading the status register clears the irqn output. an interrupt is not generated when ?no tone? is detected. dtmf rx data register bits 0 - 3 dtmf tone pairs bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) lower frequency (hz) upper frequency (hz) keypad legend 0 0 0 0 941 1633 d 0 0 0 1 697 1209 1 0 0 1 0 697 1336 2 0 0 1 1 697 1477 3 0 1 0 0 770 1209 4 0 1 0 1 770 1336 5 0 1 1 0 770 1477 6 0 1 1 1 852 1209 7 1 0 0 0 852 1336 8 1 0 0 1 852 1477 9 1 0 1 0 941 1336 0 1 0 1 1 941 1209 * 1 1 0 0 941 1477 # 1 1 0 1 697 1633 a 1 1 1 0 770 1633 b 1 1 1 1 852 1633 c a status change of the decoder and the generation of an interrupt (when the interrupt mask register bit 5 is unmasked) will occur both when a tone is first decoded and also when a tone, which was previously present, is no longer decoded. in the latter case, bit 4 of the status register will be set to ?0? to indicate that no tone was detected. the decoded tone pair is indicated by bits 0-3 in the dtmf rx data register. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 20 d/625/2 1.5.14 register set write only registers data byte structure addr. register 7 6 5 4 3 2 1 0 $1 reset n/a n/a n/a n/a n/a n/a n/a n/a $3 setup tx output buffer 0=disable 1=enable tx enable 0=disable 1=enable dtmf rx: 0=disable 1=enable spm: 0=12khz 1=16khz ring signal select [1] ring signal select [0] fsk mode: 0=sync 1=async fsk mode: 0=v23 1=bell 202 $4 mode spm o/p: 0=disable 1=enable tone/fsk: 0=disable 1=enable tone/fsk: 0=tone 1=fsk tx level: msb tx level: tx level: lsb tone fields: msb tone fields: lsb $5 tx data d7 msb d6 d5 d4 d3 d2 d1 d0 lsb $6 tx tones d7 msb d6 d5 d4 lsb d3 msb d2 d1 d0 lsb $8 iom control codec channel select [1] codec channel select [0] 0 ic channel bus reversal 0=normal 1=reverse remote digital iom loopback 0=no loopbk 1=loopback c/i1 channel output control [2] c/i1 channel output control [1] c/i1 channel output control [0] $9 int- errupt mask mask status [7] mask status [6] mask status [5] mask status [4] mask status [3] mask status [2] 0 0 $c codec control codec enable 0=disable 1=enable pcm codec: 0=a-law 1=-law local analogue loopback 0=no loopbk 1=loopback 0 0 0 0 0 read only registers data byte structure addr. register 7 6 5 4 3 2 1 0 $0 device id 1 0 0 1 1 0 0 1 $a status fsk mode: fsk tx data underflow fsk mode: fsk tx data ready dtmf rx: status change dtmf rx: 1=detected 0=no tone time out iom: tx abort iom: rx abort 0 0 $b dtmf rx data 0 0 0 0 dtmf: rx data (d3 msb) dtmf: rx data (d2) dtmf: rx data (d1) dtmf: rx data (d0 lsb) notes: 1. accessing the reset register clears all of the bits in the setup, mode, tx data, tx tones, iom control, interrupt mask, codec control, status and dtmf rx data registers and will initialise the device. this a single-byte transaction consisting of the address byte value $1. 2. if any of bits 2, 3, 4, 5, 6 or 7 of the status register is ?1? then the irqn output will be pulled low when the appropriate bit contains an unmasked logic ?1? in the interrupt mask register. 3. reading the status register clears the irqn output (when the appropriate bit contains an unmasked logic ?1? in the interrupt mask register) and also clears all the status register bits 2 to 7, if set. 1.5.15 programming the CMX625 www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 21 d/625/2 the CMX625 is programmed via the ?mon1? (monitor channel 1) channel in te mode and the ?monitor? channel in non-te mode. the programming sequence consists of 3 consecutive monitor bytes: the iom-2 address, the CMX625 command and data byte. before executing a command, the CMX625 compares the received iom-2 address byte with its own address. the msb of the iom-2 address is always a ?1? (see section 1.5.2). a logical ?1? in the msb of the CMX625 command represents a write operation and a logical ?0? represents a read operation. structure for register read/write operations: iom command register r/w 0=read 1=write 0 x x register address a3 register address a2 register address a1 register address a0 example 1: program the CMX625 to generate interrupt requests for dtmf rx status change on bit 5 of c/i channel, i.e. c/i1 channel output control code (2-0)=110. set iom-2 address to sa2-sa0=010 and device select, ds=1. mx (dd) mr (du) dd (hex) mx (du) mr (dd) du (hex) comment 1 1 ff 1 1 ff monitor channel idle state 0 1 a8 1 1 ff transmit iom-2 address 0 0 a8 1 1 ff acknowledge address 1 0 88 1 1 ff transmit command (write iom-2 control, $8) 0 1 88 1 1 ff 1 0 06 1 1 ff acknowledge command/ transmit iom-2 control data 0 1 06 1 1 ff 1 0 ff 1 1 ff acknowledge data 1 1 ff 1 1 ff end of transmission 0 1 a8 1 1 ff transmit iom-2 address 0 0 a8 1 1 ff acknowledge address 1 0 89 1 1 ff transmit command (write mask register, $9) 0 1 89 1 1 ff 1 0 20 1 1 ff acknowledge command/ transmit iom-2 control data 0 1 20 1 1 ff 1 0 ff 1 1 ff acknowledge data 1 1 ff 1 1 ff end of transmission 1 1 ff 1 1 ff idle if the command is a register read then only the address and command bytes are sent. the CMX625 will respond with an iom-2 register address byte followed by the read data. the iom-2 register address byte consists of the register address that is being read in the least significant 4 bits and the iom-2 address (less the device select bit) in the most significant 4 bits. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 22 d/625/2 example 2: read the CMX625 dtmf rx data register, d3-d0=$a. set iom-2 address to sa2-sa0 =100 and device select, ds=0. mx (dd) mr (du) dd (hex) mx (du) mr (dd) du (hex) comment 1 1 ff 1 1 ff monitor channel idle state 0 1 c0 1 1 ff transmit iom-2 address 0 0 c0 1 1 ff acknowledge address 1 0 0b 1 1 ff transmit command (write iom-2 control, $b) 0 1 0b 1 1 ff 1 0 ff 0 1 cb acknowledge command/ send address 1 1 ff 0 0 cb address acknowledged 1 1 ff 1 0 0a send dtmf read data 1 1 ff 0 1 0a 1 1 ff 1 0 ff data acknowledged 1 1 ff 1 1 ff end of transmission 1 1 ff 1 1 ff idle 1.5.16 glossary adc analogue to digital converter cidcw caller identification during call waiting codec coder/decoder dac digital to analogue converter dtmf dual tone multiple frequency fsk frequency shift keying gci general circuit interface iom-2 isdn oriented modular revision 2 isdn integrated services digital network itu international telecommunication union ntu network termination unit pc personal computer pcm pulse code modulation pots plain old (analogue) telephone service spm subscriber pulse metering ta terminal adaptor www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 23 d/625/2 1.6 application notes when using the tone/fsk bit (bit 6) of the mode register, each tone starts from v bias , and returns to v bias before ending: figure 10 tone starting and stopping when switching between tones in the same column (bits 4 - 7 or bits 0 - 3) of the tx tones register), the transition will be phase continuous. however, switching to the ?off? state will immediately take the output of that tone generator to v bias . figure 11 tone changing the tx tones register which does not have a frequency allocated is indicated by ?-? in the tone field tables. these values should not be used. 1.6.1 telecom tones the following tables give the hex codes to be programmed into the particular tone field location for various telecommunications systems applications. the tables are not exhaustive, but list the more commonly used tones. ringing signals (f 2.5%) field 0 (hz) (hex) off $00 16.7 $01 20 $02 25 $03 35 $04 40 $05 50 $06 www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 24 d/625/2 on hook ?cpe alert tones single tone field 0 dual tone field 0 (hz) (hex) (hz) (hex) 375.2 $60 375.2+1827 $6e 404.3 $70 404.3+1827 $7e 468 $80 468+1827 $8e 495.8 $90 495.8+1827 $9e 520.6 $a0 520.6+1827 $ae 548 $b0 548+1827 $be 562.8 $c0 562.8+1827 $ce 578.4 $d0 578.4+1827 $de 1633 $0d nynex (mraa) - amr alert tones (single tone) group a field 0 group b field 0 (hz) (hex) (hz) (hex) 252.4 $10 468 $80 268.7 $20 495.8 $90 285.3 $30 520.6 $a0 315.5 $40 562.8 $c0 330.5 $50 595 $e0 375.2 $60 612.5 $f0 single frequency call progress tones field 1 (hz) (hex) off $00 120 $10 150 $20 154 $30 250 $40 300 $50 350 $60 400 $c0 425 $04 440 $06 450 $07 480 $09 500 $0a 600 $0b 620 $0c www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 25 d/625/2 dual frequency call progress tones additive mixing field 1 m ultiplicative field 1 (hz) (hex) mixing (hz) (hex) off $00 350+440 $66 400*16.2 $b2 440+480 $f6 400*20 $a3 480+620 $fc 400*25 $94 400+425 $c4 400*33 $85 400+450 $c7 400*40 $76 425+450 $d4 400*50 $67 425+480 $f4 450*25 $e4 120+620 $1c 600*120 $fd 150+450 $27 dual tone multi frequency generation field 2 (hz) (hex) off $00 941+1633 $ff 697+1209 $cc 697+1336 $cd 697+1477 $ce 770+1209 $dc 770+1336 $dd 770+1477 $de 852+1209 $ec 852+1336 $ed 852+1477 $ee 941+1336 $fd 941+1209 $fc 941+1477 $fe 697+1633 $cf 770+1633 $df 852+1633 $ef special information tones, fax and modem tones and customer premises alert tones field 2 (hz) (hex) off $00 950 $80 1100 $30 1300 $40 1400 $90 1800 $a0 2100 $08 2225 $09 2130+2750 $bb www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 26 d/625/2 itu-t ?r1? signalling tones field 2 (hz) (hex) 700+900 $12 700+1100 $13 900+1100 $23 700+1300 $14 900+1300 $24 1100+1300 $34 700+1500 $15 900+1500 $25 1100+1500 $35 1300+1500 $45 700+1700 $16 900+1700 $26 1100+1700 $36 1300+1700 $46 1500+1700 $56 itu-t ?r2? signalling tones forward mode field 3 backward mode field 3 (hz) (hex) (hz) (hex) off $00 off $00 1380+1500 $89 1140+1020 $65 1380+1620 $8a 1140+900 $64 1500+1620 $9a 1020+900 $54 1380+1740 $8b 1140+780 $63 1500+1740 $9b 1020+780 $53 1620+1740 $ab 900+780 $43 1380+1860 $8c 1140+660 $62 1500+1860 $9c 1020+660 $52 1620+1860 $ac 900+660 $42 1740+1860 $bc 780+660 $32 1380+1980 $8d 1140+540 $61 1500+1980 $9d 1020+540 $51 1620+1980 $ad 900+540 $41 1740+1980 $bd 780+540 $31 1860+1980 $cd 660+540 $21 www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 27 d/625/2 1.7 performance specification 1.7.1 electrical performance 1.7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current into or out of v dd and v ss pins -50 +50 ma current into or out of any other pin -20 +20 ma d5 package min. max. unit total allowable power dissipation at tamb = 25c - 550 mw ... derating - 9 mw/c storage temperature -55 +125 c operating temperature -40 +85 c p4 package min. max. unit total allowable power dissipation at tamb = 25c - 800 mw ... derating - 13 mw/c storage temperature -55 +125 c operating temperature -40 +85 c 1.7.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. unit supply (v dd - v ss ) 2.7 5.5 v operating temperature -40 +85 c www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 28 d/625/2 1.7.1.3 operating characteristics for the following conditions unless otherwise specified: v dd = 2.7v at tamb = 25c and v dd = 3.0v to 5.5v at tamb = -40 to +85c, 0dbm = 775mvrms = 0dbm0. dc parameters notes min. typ. max. unit i dd all enabled, v dd = 5.0v 1 - 6.9 - ma all disabled, v dd = 5.0v 1 - 140 - a dtmf rx only, v dd = 5.0v 1 - 2.4 - ma tx (tones, spm) only, v dd = 5.0v 1 - 3.5 - ma tx output buffer only enabled, v dd = 5.0v 1 - 1.8 - ma pcm codec only, v dd = 5.0v 1 - 3.1 - ma all enabled, v dd = 3.3v 1 - 5.0 - ma all disabled, v dd = 3.3v 1 - 80 - a dtmf rx only, v dd = 3.3v 1 - 1.6 - ma tx (tones, spm) only, v dd = 3.3v 1 - 2.3 - ma tx output buffer only enabled, v dd = 3.3v 1 - 1.3 - ma pcm codec only, v dd = 3.3v 1 - 2.3 - ma logic ?1? input level (cmos inputs) 3 70% - - v logic ?0? input level (cmos inputs) 3 - - 30% v logic input leakage current (vin = 0 to v dd ) 3 -1.0 - +1.0 a logic ?1? input level (ttl inputs) 3 2.0 - - v logic ?0? input level (ttl inputs), vdd = 3.3v-5.5v 3, 13 - - 0.8 v output logic ?1? level dd, du (i oh = 4ma) 14 0.8 - - v dd output logic ?0? level dd du (i ol = 6ma) 14 - - 0.4 v output logic ?0? level irqn (i ol = 3ma) 14 - - 0.4 v irqn o/p ?off state current (v out = v dd ) - - 1.0 a fsk encoder and tx uart notes min. typ. max. unit level at tonefsk pin 4 -1.0 0 1.0 dbm twist (mark level w.r.t. space level) -2.0 0 +2.0 db tx 1200bits/sec (v23 mode) baud rate (set by uart and dcl) 1194 1200 1206 baud mark (logical 1) frequency 1297 1300 1303 hz space (logical 0) frequency 2097 2100 2103 hz tx 1200bits/sec (bell 202 mode) baud rate (set by uart and dcl) 1194 1200 1206 baud mark (logical 1) frequency 1197 1200 1203 hz space (logical 0) frequency 2197 2200 2203 hz tonefsk signal level notes min. typ. max. unit level at tonefsk pin for: single tone 4 -1.0 0 1.0 dbm dual tone (per tone) 4 -4.0 -3.0 -2.0 dbm dtmf high frequency group 4 -4.0 -3.0 -2.0 dbm dtmf low frequency group 4 -6.0 -5.0 -4.0 dbm output impedance - 10.0 - k ? tone frequency resolution -2.5 - 2.5 hz tone output distortion 5 - 0.8 - % www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 29 d/625/2 dtmf decoder notes min. typ. max. unit valid input signal levels (each tone of composite signal) 4 -29.0 - -2.0 dbm not decode level (either tone of composite signal) 4 - - -40.0 dbm twist = high tone/low tone -9.0 - 10.0 db frequency detect bandwidth 1.8 - 4.5 % dial tone tolerance 6 - - 0 db noise tolerance 6,7 - -14 - db tone response time 2 - - 40.0 ms tone de-response time 2 - - 45.0 ms tone burst detected 2 40.0 - - ms tone burst ignored 2 - 20.0 - ms pause length detected 2 40.0 - - ms pause length ignored 2 - - 20.0 ms spm signal level notes min. typ. max. unit level at spm pin 4, 9 -1.5 0 1.0 dbm 4, 9, 10 -1.0 0 0.5 db tone frequency accuracy -14.0 - 14.0 hz tone output distortion 5 - 1.2 - % output impedance - 10.0 - k ? pcm codec-filter notes min. typ. max. unit pcm codec-filter passband 8 300 - 3400 hz passband gain (at 1.02khz) 8 - 0 - db passband ripple (w.r.t. gain at 1.02khz) 8 -0.5 - +0.5 db stopband attenuation 8 - 30.0 - db group delay absolute - - 600 s relative to 1khz: 500hz - - 1.5 ms 600hz - - 0.75 ms 2600hz - - 0.25 ms 2800hz - - 1.5 ms signal-to-total distortion ratio as a function of input level (1khz input level): -45dbm 11 22.0 - - dbp -40dbm 11 27.0 - - dbp -30dbm 11 33.0 - - dbp 0dbm 11 33.0 - - dbp variation of gain with input level (1khz input signal) -55dbm0 -3.0 - +3.0 db -50dbm0 -1.0 - +1.0 db -40dbm0 -0.5 - +0.5 db +3dbm0 -0.5 - +0.5 db idle channel noise 11 - - -65.0 dbm0p output impedance - 1.0 - k ? www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 30 d/625/2 tx output buffer notes min. typ. max. unit buffer output signal swing; 12 2.2 - - vp-p load greater than 500 ? power-up timing notes min. typ. max. unit device reset to reliable signal at txo, txon, - 50.0 - ms ring, spm or tonefsk output pins notes: 1. at 25 c, not including any current drawn from the CMX625 pins by external circuitry. 2. at nominal signal frequencies and without skew. 3. excluding iom-2 serial bus interface pins: fsc, dcl, dd and du in bus reversal. 4. at v dd = 5.0v, load resistance greater than 40k ? , signal levels are proportional to v dd . 5. frequency above 300hz. 6. referenced to dtmf tone of lower amplitude. 7. bandwidth limited: 0 to 3.4khz gaussian noise. 8. see filter response, figure 12. 9. spm has a soft rise and fall time of about 4ms. the level changes between v bias and 0dbm in 2db steps, 16 steps per rise and fall. when spm is disabled, an extra 4ms falling tail end of signal should be taken into consideration. 10. over the range v dd = 3.3v to 5.5v at tamb = 25c. 11. represents a psophometrically weighted measurement. 12. for each of the txon (if enabled) and txo pins, load placed between the pin and v dd / 2, for v dd = 5.0v only. 13. derate linearly minimum ttl logic ?0? level from 0.8v at vdd = 3.3v to 0.5v at vdd = 2.7v. 14. all outputs cmos levels. www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 31 d/625/2 -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0 500 1000 1500 2000 2500 3000 3500 frequency (hz) figure 12a passband - pcm codec-filter overall frequency response -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 1000 2000 3000 4000 5000 6000 7000 8000 frequency (hz) gain (db) figure 12b pcm codec-filter overall frequency response www.datasheet.in
isdn ta pots interface CMX625 ? 2001 consumer microcircuits limited 32 d/625/2 iom-2 bus timing (see figure 13) notes min. typ. max. unit t dcl dcl clock period in te mode 1 - 651 - ns t dcl dcl clock period in non-te mode 1 - 244 - ns t r / t f dcl clock rise time / fall time 1 - - 60 ns fsc fsc period 1 - 125 - s t fscs fsc set-up time 1 70 - - ns t fsch fsc hold time 1 40 - - ns t dudc du delay clock (data out) 2 - - 100 ns t dudf du delay frame (data out) 2 - - 150 ns notes: 1. these signals are requirements and are not under control of CMX625. 2. condition c l = 150pf. figure 13 iom-2 bus timing diagram typical uart timings (see figures 9a and 9b) notes min. typ. max. unit t fsk (delay through the modulator) - 106 - s t dly (1 bit period) - 833 - s t drdy (? bit-period) - 208 - s t ufl (? bit-period) - 625 - s www.datasheet.in
isdn ta pots interface CMX625 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circu it patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with thi s product specification. specific testing of all circuit parameters is not necessarily performed. oval park - langford maldon - essex cm9 6wg - england telephone: +44 (0)1621 875500 telefax: +44 (0)1621 875600 e-mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk 1.7.2 packaging figure 12 24-pin ssop (d5) mechanical outline: order as part no. CMX625d5 figure 13 24-pin dil (p4) mechanical outline: order as part no. CMX625p4 www.datasheet.in
cml product data in the process of creating a more global image, the three standard product semiconductor companies of cml microsystems plc (consumer microcircuits limited (uk), mx-com, inc (usa) and cml microcircuits (singapore) pte ltd) have undergone name changes and, whilst maintaining their separate new names (cml microcircuits (uk) ltd, cml microcircuits (usa) inc and cml microcircuits (singapore) pte ltd ), now operate under the single title cml micro- circuits . these companies are all 100% owned operating companies of the cml microsystems plc group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. cml microcircuits product prefix codes until the latter part of 1996, the differentiator between products manufactured and sold from mxcom, inc. and consumer microcircuits limited were denoted by the prefixes mx and fx respectively. these products use the same silicon etc. and today still carry the same prefixes. in the latter part of 1996, both companies adopted the common prefix: cmx. this notification is relevant product information to which it is attached. company contact information is as below: cml microcircuits (uk)ltd communication semiconductors cml microcircuits communication semiconductors cml microcircuits (singapore)pteltd communication semiconductors cml microcircuits (usa) inc. communication semiconductors oval park, langford, maldon, essex, cm9 6wg, england tel: +44 (0)1621 875500 fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com 4800 bethania station road, winston-salem, nc 27105, usa tel: +1 336 744 5050, 0800 638 5577 fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com no 2 kallang pudding road, 09-05/ 06 mactech industrial building, singapore 349307 tel: +65 7450426 fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com d/cml (d)/1 february 2002 www.datasheet.in

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